NXP Semiconductors /MIMXRT1011 /IOMUXC /SW_MUX_CTL_PAD_GPIO_AD_05

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Interpret as SW_MUX_CTL_PAD_GPIO_AD_05

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ALT0)MUX_MODE 0 (DISABLED)SION

SION=DISABLED, MUX_MODE=ALT0

Description

SW_MUX_CTL_PAD_GPIO_AD_05 SW MUX Control Register

Fields

MUX_MODE

MUX Mode Select Field.

0 (ALT0): Select mux mode: ALT0 mux port: LPSPI1_PCS0 of instance: LPSPI1

1 (ALT1): Select mux mode: ALT1 mux port: PIT_TRIGGER01 of instance: PIT

2 (ALT2): Select mux mode: ALT2 mux port: FLEXPWM1_PWM3_B of instance: FLEXPWM1

3 (ALT3): Select mux mode: ALT3 mux port: KPP_ROW01 of instance: KPP

4 (ALT4): Select mux mode: ALT4 mux port: GPT2_CAPTURE1 of instance: GPT2

5 (ALT5): Select mux mode: ALT5 mux port: GPIOMUX_IO19 of instance: GPIOMUX

SION

Software Input On Field.

0 (DISABLED): Input Path is determined by functionality

1 (ENABLED): Force input path of pad GPIO_AD_05

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